As device size shrinks down aggressively in advanced very large scale integration (VLSI) technology, increased process variation causes significant amounts of threshold voltage fluctuation. As a result, stability of static random access memory (SRAM) deteriorates due to the large threshold voltage mismatch between two neighboring transistors in a cell. The conventional 6-transistor (6T) SRAM 100, depicted in FIG. 1, includes a first inverter formed by p-type and n-type field effect transistors (PFET and NFET, respectively) PL and NL (numbered 102 and 104), cross-coupled to a second inverter formed by PFET PR and NFET NR, numbered 106, 108. The cross-coupled inverters are connected to a voltage supply node 110 and a ground 112. Left and right NFET access devices AL, AR, numbered 114 and 116, inter connect true bit line 118 and complementary bit line 120 to storage nodes Qb (numbered as 126) and Q (numbered as 124), respectively, under control of word line 122.
Cell 100 has its worst stability during the READ mode because the voltage at the storage node which has a “0” logic value (node Q numbered as 124, in FIG. 1) goes up during the READ cycle. If the increased node voltage is larger than the trip voltage of the inverter formed by the PL-NL pair (FETs 102 and 104), the stored logic values will be flipped and data will be lost.
Turning now to FIG. 2, a memory cell 200 with decoupled READ and WRITE bit lines (that is, a single-end READ eight transistor (8T) SRAM cell) has been proposed to make the memory cell stable in READ mode. See L. Chang et. al, “Stable SRAM Cell Design for the 32 nm Node and Beyond,” VLSI technology symp. 2005. Another pertinent prior art application is set forth in U.S. Pat. No. 6,279,144 to Henkels et al., entitled “Provably Correct Storage Arrays.” With continued reference to FIG. 2, note that elements therein similar to those in FIG. 1 have received the same reference character incremented by one hundred and will not be described again except to the extent that they differ substantially from the corresponding elements in FIG. 1. True and complementary WRITE bit lines 218, 220 are provided as before and access devices 214, 216 selectively connect the inverters to them under the control of WRITE word line 222. However, a separate READ word line 228 is provided, and node 224 is connected to the gate of one of two series read access devices, for example, NFETS 232, 234, with the gate of the other series FET connected to READ word line 228. When a high logic level is present on READ word line 228 and node 224, both NFETS 232 and 234 turn on to connect READ bit line 230 to ground node 236.
Although the memory cell 200 with decoupled READ and WRITE is stable in the READ mode, it is still unstable in a “Half-Select” condition during the WRITE mode, if cells are interleaved along a word line (interleaving is discussed below).
It would be desirable to overcome the limitations in previous approaches.